1. Field of the Invention
This invention relates to a signal processing device and more particularly to control over the level of a digital signal reproduced from a recording medium.
2. Description of Related Art
It has been known to arrange an apparatus such as a digital VTR or the like which transmits data at a high speed (for recording or reproduction) to use a phase locked loop (hereinafter referred to as PLL) in extracting a clock signal from a data train received.
Further, in the field of digital VTRs of the kind performing high density magnetic recording, a detecting method called a xe2x80x9cpartial response 1,0,xe2x88x921 method of systemxe2x80x9d (hereinafter referred to as the PR(1,0,xe2x88x921) system) has come to be popularly employed in detecting reproduced data.
FIG. 1 is a block diagram showing by way of example the arrangement of the reproduction system of a digital VTR of the above-stated kind. Referring to FIG. 1, a digital signal recorded on a magnetic tape 1 is reproduced by a magnetic head 2. The amplitude of the reproduced digital signal is controlled by a gain control amplifier (GCA) 3 and is then supplied to a reproduction equalizing circuit 4. In a case where a longitudinal recording medium and a ring-type magnetic head are in combination, the reproduction frequency characteristic of the magnetic head 2 is as shown in FIG. 2(a). As shown, a differential characteristic is obtained for a low frequency band while an attenuating characteristic is obtained for a high frequency band due to losses of varied kinds. To solve this problem, the reproduction equalizing circuit 4 which has a frequency characteristic as shown in FIG. 2(b) is used for equalization to make the frequency characteristic into a cosine roll-off characteristic as shown in FIG. 2(c). The cosine roll-off characteristic minimizes a waveform interference at a data detecting point. The recorded data is restored by carrying out a binary discriminating action on the equalized signal.
The equalizing process described above is called an integral equalization and a process of detecting the polarity of the integrally equalized signal by means of comparator or the like is called integral detection.
The eye pattern of the signal which is integrally equalized in the above-stated manner becomes as shown in FIG. 3(a). In order to accurately detect the data, it is necessary to generate such a clock signal that permits accurate sampling at a point where a maximum eye opening is obtained. This clock signal is generated by a PLL (phase-locked loop) which consists of a phase detecting circuit 22, a loop filter 21 and a voltage controlled oscillator 20 (hereinafter referred to as VCO).
A phase difference between the clock signal generated by the VCO 20 and a signal outputted from the reproduction equalizing circuit 4 is detected by the phase detecting circuit 22. A phase difference signal thus obtained is supplied through the loop filter 21 to the VCO 20 to apply a phase lock by controlling the oscillation frequency of the VCO 20 in such a way as to make the phase difference almost zero at the phase detecting circuit 22. Further, in this instance, the phase response characteristics of the PLL such as the frequency characteristic of the loop filter 21, a gain, the sensitivity of the VCO 20, etc., are set in such a way as to adequately absorb jitters generated by the head-tape system of the VTR and not to readily respond to noises of varied kinds.
With a PLL arranged to obtain a clock signal for an A/D converter 5 in the above-stated manner, a point at which a maximum eye opening is obtained can be sampled by adjusting the phase of the lock of the PLL, for example, by adjusting the operating point of the phase detecting circuit 22. Further, in order to correctly detect data, the amplitude of the signal at the point of detection must be kept unvarying. To meet this requirement, an automatic gain control loop (hereinafter referred to as AGC loop) is formed with an amplitude detecting circuit 23, a loop filter 24 and the GCA 3.
The amplitude detecting circuit 23 includes a detection circuit which is arranged to detect the peak value of the signal equalized. The detected peak value is amplified when only a low band component of the signal is passed by the loop filter 24 and is supplied to the control terminal of the GCA 3. The gain of the GCA 3 is thus controlled to keep the amplitude detection output almost constant.
The integrally equalized signal is sampled by the A/D converter 5 under the control of the clock signal generated by the above-stated PLL and is converted into a digital signal which consists of a plurality of bits per sample thus obtained. The signal reproduced by the head 2 is of course in the form of a digital signal. However, the amplitude of the digital signal varies in an analog manner. Therefore, the A/D converter 5 converts the reproduced signal again into a digital signal consisting of a plurality of bits per sample as mentioned above.
The reproduced signal which has been converted into the digital signal is delayed by a delay circuit 6 as much as the length of two clock pulses to obtain a delayed signal. The delayed signal is subtracted from the original signal by a subtracter 7. Through this process, the integrally equalized waveform is converted into a waveform having the characteristic of PR(1,0,xe2x88x921) and its eye pattern has a ternary value as shown in FIG. 3(b).
This signal of the PR(1,0,xe2x88x921) characteristic is supplied to a Viterbi decoding circuit 8 to be restored to the original form of binary signal of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d by maximum likelihood decoding. In other words, the signal is outputted as a digital signal having one bit per sample.
The combination of the PR(1,0,xe2x88x921) method and the Viterbi decoding is often used for a digital VTR arranged to perform high density magnetic recording. The use of this combination enables the VTR to avoid the degradation of the low band characteristic of a magnetic recording system, such as deteriorated S/N ratio and distorted waveform, and to minimize transmission errors. The reproduced data decoded by the Viterbi decoding circuit 8 is supplied to an error correcting circuit (ECC) 9 to have any error generated through a transmission route corrected by using parity data added to the signal at the time of recording. The corrected data is supplied to an image decoding circuit 10. The image decoding circuit 10 expands the amount of information of the reproduced data which has been compressed at the time of recording and then supplies its output to a D/A converter 11. The D/A converter 11 then converts the input digital data into analog data. The analog data thus obtained is outputted through an output terminal 12.
To keep the integrally equalized reproduced signal at a constant amplitude, the conventional VTR described above is arranged to peak-detect the amplitude of the equalized signal and to perform control in such a way as to keep its detection output unvarying.
However, as apparent from the eye patterns shown in FIGS. 3(a) and 3(b), the arrangement of carring out the peak detection tends to keep unvarying an amplitude obtained at some point other than a desired detection point at which the amplitude is desired to be kept unvarying. The peak voltage of the point other than the detection point varies too much depending on the pattern of data. Particularly, in the case of the waveform obtained by integrally equalizing the signal reproduced by a magnetic recording/reproduction system, a low frequency noise is superimposed on the waveform. The detected amplitude is inevitably affected by the low frequency noise to make it difficult to keep the amplitude level unvarying.
According to the conventional method, therefore, errors of reproduced data tend to increase as the data cannot be accurately detected.
It is a principal object of this invention to solve the problem of the prior art described above.
It is a more specific object of this invention to provide a signal processing device which is arranged to be capable of accurately keeping a reproduced signal at a desired level according to a data detecting point and to lessen the error of reproduced data.
Under this object, a digital signal processing device according to this invention includes pattern detecting means for detecting a specific pattern included in an input digital signal, level detecting means for detecting the level of the input digital signal on the basis of an output of the pattern detecting means, and level control means for controlling the level of the input digital signal according to the output of the level detecting means.
It is another object of this invention to provide a device which is simply arranged to be capable of controlling in an optimum manner the level of a signal obtained at a data detecting point.
It is a further object of this invention to provide a device which is simply arranged to be capable of controlling in an optimum manner the level of a signal obtained at a data detecting point and to accurately detect any phase variations of an input signal.
These and other objects and features of this invention will become apparent from the following detailed description of embodiments thereof taken in connection with the accompanying drawings.